Researchers from RPTU Kaiserslautern-Landau and UC San Diego published a paper titled 'FastPath: A Hybrid Approach for Efficient Hardware Security Verification.'
The paper introduces a hybrid verification methodology called FastPath that combines simulation efficiency with formal verification thoroughness to address hardware security issues.
FastPath automates the verification process using a structural analysis framework, reducing manual effort while achieving exhaustive confidence levels. It also identified and provided a fix for a security leak in a RISC-V processor.
The paper was presented at DAC and offers an innovative approach to hardware security verification, improving efficiency and thoroughness simultaneously.