A technical paper titled 'Garblet: Multi-party Computation for Protecting Chiplet-based Systems' was published by Worcester Polytechnic Institute.
The paper presents Garblet, a framework that combines chiplet technology and Garbled Circuits (GC)-based Multi-party Computation (MPC) to enable secure computation in the presence of potentially compromised chiplets.
Garblet integrates a customized hardware Oblivious Transfer (OT) module and an optimized evaluator engine into chiplet-based platforms, reducing communication costs and enhancing computation speed.
The framework was implemented on an AMD/Xilinx UltraScale+ multi-chip module, showing promising results in terms of security, privacy, and computational efficiency.