3D IC heterogeneous integration, a system approach, disaggregates what would be implemented as an SoC into chiplets for improved performance at reduced cost and higher yield.
System Technology Co-optimization (STCO) involves architectural planning, analysis, physical design, and electrical and reliability analysis in 3D IC design.
The Chiplet Design Exchange (CDX) established within the Open Compute Project aims to promote 3D IC technology and create a chiplet ecosystem.
The CDX group consists of EDA vendors, FABs, OSATs, and substrate material providers working on design kits for 3D IC integration.
To support 3D IC design, four 3DKs are being developed: Chiplet Design Kits (CDK), Package Assembly Design Kits (PADK), Material Design Kits (MDK), and Package Test Design Kits (PTDK).
CDK models are recommended for early planning and design, while PADK defines pitch spacing rules and material properties are defined by MDKs.
MDKs provide material properties for thermal, stress, and signal integrity analysis, while PTDKs define test IO pins and functions.
The 3DK models enable chiplet ecosystem development, allowing chiplet suppliers to describe their products and enable designers to choose suitable parts.
The CDX group is working on authoring tools to create 3DK models in a machine-readable, open-source EDA-neutral format to propel 3D IC integration into mainstream design.
Innovator3D IC by Siemens EDA offers a multi-physics cockpit for 3D IC design and manufacturing, facilitating planning and heterogeneous integration of ASICs and chiplets.