<ul><li>The paper introduces ATHEENA, a Toolflow for Hardware Early-Exit Network Automation.</li><li>ATHEENA leverages the probability of samples exiting early to optimize resource allocation in FPGA networks.</li><li>The toolflow uses data-flow model and Design Space Exploration to improve throughput and reduce area while maintaining accuracy.</li><li>Experimental results show throughput increase and resource reduction in comparison to baseline network implementations.</li></ul>

ATHEENA: A Toolflow for Hardware Early-Exit Network Automation

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