<ul data-eligibleForWebStory="false"><li>Researchers propose a deep-learning-based model for predicting parasitic capacitance in pre-layout stages of SRAM designs to enhance system energy efficiency.</li><li>The model utilizes a Graph Neural Network (GNN) classifier and Multi-Layer Perceptron (MLP) regressors to accurately predict parasitics in SRAM circuits.</li><li>Experiments on 4 real SRAM designs demonstrate that the proposed approach outperforms the state-of-the-art model, reducing prediction error by up to 19 times and speeding up the simulation process by up to 598 times.</li></ul>

Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs

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