<ul><li>Efficient neural networks (NNs) using lookup tables (LUTs) have shown potential for AI applications on FPGAs.</li><li>NeuraLUT-Assemble is a framework that combines mixed-precision techniques and assembly of larger neurons to improve accuracy and connectivity of LUT-based designs.</li><li>It introduces skip-connections to enhance gradient flow and achieves competitive accuracy in various tasks.</li><li>NeuraLUT-Assemble also demonstrates up to 8.42x reduction in the area-delay product compared to the state-of-the-art at the time of publication.</li></ul>

NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference

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