<ul><li>A study explores methods to optimize testing in semiconductor manufacturing for wafer and FPGA testing to reduce costs while maintaining accuracy.</li><li>Baseline sampling strategies like Random Sampling, Stratified Sampling, and k-means Clustering Sampling are investigated, with the introduction of novel algorithms to enhance sampling quality.</li><li>Hybrid strategies, Stratified with Short Distance Elimination (S-SDE) and k-means with Short Distance Elimination (K-SDE), show improved performance in predicting wafer and FPGA test data.</li><li>Experimental results indicate that the proposed SDE-based strategies enhance predictive accuracy, with K-SDE improving k-means sampling by 16.26% for wafer testing and 13.07% for FPGA testing.</li></ul>

Optimizing FPGA and Wafer Test Coverage with Spatial Sampling and Machine Learning

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