<ul><li>Large language models have transformed hardware design but bridging the gap between code synthesis and PPA estimation remains a challenge.</li><li>A novel framework is introduced to predict power, performance, and area (PPA) metrics from Verilog code.</li><li>The framework utilizes chain-of-thought techniques to clean and curate a dataset of synthesizable Verilog modules.</li><li>Experimental results show significant improvements in power, delay, and area estimation using the proposed framework.</li></ul>

RocketPPA: Ultra-Fast LLM-Based PPA Estimator at Code-Level Abstraction

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