<ul><li>Researchers propose a two-stage hardware-aware neural architecture search (HW-NAS) framework for optimizing the performance of target devices.</li><li>The first stage involves training an architecture controller on synthetic devices.</li><li>The second stage deploys the learned controller on the target device, without relying on pre-collected information.</li><li>The framework enables the controller to design architecture for the target device through high-fidelity latency measurements and in-context adaptation.</li></ul>

Sim-is-More: Randomizing HW-NAS with Synthetic Devices

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